Digital Phase-Locked Loop (DPLL) All-Digital Phase-Locked Loop Working Principle

The basic operation of a fully digital phase-locked loop is as follows:

(1) The input signal Ui(t) and the local oscillator signal (digital voltage-controlled oscillator output signal) Uo(t) are sinusoidal and cosinusoidal signals, respectively, which are compared within the digital phase-discriminator, and the output of the digital phase-discriminator is a voltage Ud(t) that is proportional to the phase difference between the two.

(2) Digital loop filter in addition to the high-frequency component of the digital phase discriminator output, and then the output voltage Uc (t) added to the input of the digital voltage-controlled oscillator, the digital voltage-controlled oscillator of the fundamental oscillator signal frequency with the input voltage changes. If the two frequencies do not coincide, the output of the digital phase discriminator will generate a low-frequency change component and pass through a low-pass filter to change the frequency of the DCO. As long as the loop is properly designed, this change will cause the frequency of the local oscillator signal Uo(t) to coincide with the frequency of the digital discriminator input signal Ui(t).

(3) Finally, if the frequency of the local oscillator signal and the frequency of the input signal are exactly the same, and the phase difference between the two will remain at a constant value, then the output of the digital phase discriminator will be a constant DC voltage (ignoring the high-frequency component), and the output of the digital loop filter will also be a DC voltage, and the frequency of the DCO will stop changing. "locked state".