The development of ddr memory sticks has gone through several eras they are those eras!

Memory is one of the most important parts of the computer, it is the bridge to communicate with the CPU. All the programs in the computer are running in the memory, so the performance of the memory has a very big impact on the computer. In this article, we will talk about the history of memory development, and by the way, compare the difference between the various stages of memory.

First, DDR

DDR = Double Data Rate double speed memory. Strictly speaking, DDR should be called DDR SDRAM, people used to call it DDR, part of the beginner also often see DDR SDRAM, think it is SDRAM. DDR SDRAM is the abbreviation of Double Data Rate SDRAM, is the meaning of Double Rate Synchronous Dynamic Random Access Memory (DDRSRAM). DDR memory is developed on the basis of SDRAM memory. DDR memory is based on SDRAM memory, and still follows the SDRAM production system. Therefore, for memory manufacturers, they only need to slightly improve the equipment for manufacturing ordinary SDRAM to realize the production of DDR memory, which can effectively reduce the cost.

SDRAM transmits data only once during a clock cycle, during the rise of the clock, while DDR memory transmits data twice during a clock cycle, once during the rise of the clock and once during the fall of the clock, and is therefore called double-rate synchronous dynamic random memory. DDR memory can achieve higher data transfer rates at the same bus frequency as SDRAM.

Compared with SDRAM: DDR utilizes more advanced synchronization circuits that allow the main steps of specifying the address, transporting data, and outputting the data to be executed independently while remaining fully synchronized with the CPU; DDR uses DLL (Delay Locked Loop to provide a data filtering signal) technology, which allows the memory controller to use the data filtering signal to accurately locate the data when the data is valid. When data is valid, the data filter signal can be used by the memory controller to accurately position the data, output every 16th time, and resynchronize the data from the different memory modules. ddr essentially doubles the speed of sdram without increasing the clock frequency, promising to read out the data on both the rising and falling edges of the clock pulse, and is therefore twice as fast as standard sdram.

There is not much difference between DDR and SDRAM in terms of form factor, as they are the same size and have the same pin distance. But at 184 pins, DDR has 16 more pins than SDRAM and contains mainly new signals for control, clock, power and ground.DDR memory uses the SSTL2 standard, which supports 2.5V, rather than the 3.3V LVTTL standard used by SDRAM.

The frequency of DDR memory can be expressed in terms of both the operating frequency and the equivalent frequency. The operating frequency is the actual frequency at which the memory grains operate, but since DDR memory can transmit data on both the rising and falling edges of the pulse, the equivalent frequency for transmitting data is twice the operating frequency.

Two, DDR2

DDR2 invention and development:

DDR2/DDR II (Double Data Rate 2) SDRAM is a new generation of memory technology standard developed by JEDEC (Joint Electron Device Engineering Council), which is different from the previous generation of DDR memory technology standard. The major difference between SDRAM and the previous generation of DDR memory technology standard is that, although it adopts the same basic method of transferring data at the same time as the rising/falling delay of the clock, DDR2 memory has twice the pre-reading capability (i.e., 4-bit data read pre-fetching) of the previous generation of DDR memory. In other words, DDR2 memory is capable of reading/writing data at 4x the speed of the external bus per clock, and can run at 4x the speed of the internal control bus.

In addition, as the DDR2 standard specifies that all DDR2 memory is to be packaged in an FBGA package, unlike the widely used TSOP/TSOP-II packages, the FBGA package offers better electrical performance and heat dissipation, providing a solid foundation for stable operation and future frequency development of DDR2 memory. Recalling the development history of DDR, from the first generation of DDR200 applied to personal computers through DDR266, DDR333 to today's dual-channel DDR400 technology, the development of the first generation of DDR has come to the limit of the technology, it has been difficult to improve the working speed of memory through conventional methods; with the development of Intel's newest processor technology, the front-end bus requirements for memory bandwidth are getting higher and higher, with higher and higher bandwidth. With Intel's latest processor technology, the front end bus requires more and more memory bandwidth, and DDR2 memory will be the trend.

Differences between DDR2 and DDR:

1. Latency:

At the same core frequency, the actual operating frequency of DDR2 is twice that of DDR. This is due to the fact that DDR2 memory has twice the 4BIT pre-read capability of standard DDR memory. In other words, while DDR2, like DDR, utilizes the basic method of transferring data at both the rising and falling delays of the clock, DDR2 has twice the ability to pre-read system command data. That is, at the same 100MHz operating frequency, DDR's actual frequency is 200MHz, while DDR2 can go up to 400MHz.

This also brings up another issue: among DDR and DDR2 memories operating at the same frequency, the latter's memory latency is slower than that of the former. For example, DDR 200 and DDR2-400 have the same latency, while the latter has twice the bandwidth. In fact, DDR2-400 and DDR 400 have the same bandwidth, they are both 3.2GB/s, but DDR400's core operates at 200MHz while DDR2-400's core operates at 100MHz, which means that the latency of DDR2-400 is higher than that of DDR400.

2. Packaging and heat generation:

The biggest breakthrough in DDR2 memory technology is actually not in the users' perception of twice the transfer capability of DDR, but in the adoption of lower heat generation and lower power consumption, DDR2 can get a faster frequency increase, breaking through the 400MHz limit of standard DDR.

DDR memory is usually packaged in TSOP chip packages, which work well at 200MHz. When the frequency is higher, its long pins create high impedance and parasitic capacitance, which affects its stability and makes it harder to boost frequencies. This is the reason why the core frequency of DDR is difficult to break through 275MHZ. DDR2 memory is packaged in FBGA. Unlike the widely used TSOP package, the FBGA package offers better electrical performance and heat dissipation, providing a better guarantee for the stability of DDR2 memory and future frequency development.

DDR2 memory uses 1.8V, a significant reduction from the standard DDR 2.5V, to provide significantly lower power consumption and lower heat generation, a change that is significant.

New technologies adopted by DDR2:

In addition to the differences mentioned above, DDR2 introduces three new technologies, which are OCD, ODT, and Post CAS.

1. OCD (Off-Chip Driver): Also known as Off-Chip Driver Tuning, the DDR II is able to improve signal integrity through OCD. The DDR II equalizes the two voltages by adjusting the value of the pull-up/pull-down resistors. Using OCD improves signal integrity by reducing the DQ-DQS skew; signal quality is improved by controlling the voltage.

2. ODT: ODT is the termination resistor for the built-in core. We know that motherboards using DDR SDRAM need a lot of termination resistors on top in order to prevent the signal from being reflected at the end of the data lines. It greatly increases the manufacturing cost of the motherboard. In fact, different memory modules have different requirements for termination circuits. The size of the termination resistor determines the signal-to-noise ratio and reflectivity of the data line; a small termination resistor results in a low signal-to-noise ratio for the data line, while a high termination resistor results in a high signal-to-noise ratio for the data line, but signal reflectivity will also increase. Therefore, the termination resistor on the motherboard does not match the memory module very well and affects the signal quality to a certain extent, while DDR2 can be built-in with suitable termination resistor according to its own characteristics, which can ensure the best signal waveform. Using DDR2 not only reduces the cost of the motherboard, but also provides the best signal quality, which is unmatched by DDR.

3. Post CAS: It is designed to improve the utilization of DDR II memory. In Post CAS operation, the CAS signal (read/write/command) can be inserted one clock cycle behind the RAS signal, and the CAS command can be kept active behind the Additive Latency. The original tRCD (RAS to CAS and delay) is replaced by AL (Additive Latency), which can be set in 0, 1, 2, 3, 4. Since the CAS signal is placed one clock cycle after the RAS signal, the ACT and CAS signals will never collide and conflict.

Three, DDR3

Development

As early as June 28, 2002, JEDEC announced the start of the development of the DDR3 memory standard, but judging from the current situation, the DDR2 has just begun to popularize, the DDR3 standard is even more did not even see the shadow. However, many manufacturers have already come up with their own DDR3 solutions, and have announced the successful development of DDR3 memory chips, from which we seem to be able to feel the footsteps of DDR3 approaching. And from the point of view that there are already chips that can be produced, the standard design work of DDR3 is also close to completion.

Semiconductor market researcher iSuppli speculates that DDR3 memory will replace DDR2 as the dominant product in the market in 2008, and iSuppli believes that DDR3's market share will reach 55 percent at that time. However, as far as specific designs are concerned, the underlying architecture of DDR3 is not fundamentally different from that of DDR2. In some ways, DDR3 was spawned to address the limitations faced by DDR2 development.

Difference between DDR2 and DDR3

The generation of memory technology for Intel's new chips (but currently mainly used for graphics memory), with a frequency of 800M or more, has the following advantages over DDR2:

(1) Less power consumption and heat generation: Drawing on the lessons learned from DDR2, DDR3 has reduced power consumption and heat generation while controlling costs. This makes DDR3 more accessible to users and manufacturers.

(2) Higher operating frequency: Due to lower power consumption, DDR3 can achieve higher operating frequency, which can make up for the longer latency to a certain extent, and can also be used as one of the selling points of graphics cards, which has already been shown in the graphics cards with DDR3 memory.

(3) Reducing the overall cost of graphics cards: DDR2 memory particles are mostly 4M X 32bit, and with the 128MB memory commonly used in mid-range and high-end graphics cards, you will need 8 of them. DDR3 memory specifications are mostly 8M X 32bit, single particle capacity is larger, 4 can constitute 128MB memory. In this way, the graphics card PCB area can be reduced, the cost can be effectively controlled, in addition, the number of particles to reduce the number of memory power can be further reduced.

(4) Good versatility: Compared to the change from DDR to DDR2, DDR3 has better compatibility with DDR2. As the pinout, packaging and other key features remain unchanged, graphics cards with DDR2 display cores and public design can adopt DDR3 memory with a little modification, which is good for manufacturers to reduce costs.

At present, DDR3 memory is widely used in most new mid-range and high-end graphics cards.

Design Scale

I. DDR3 adopts a new design based on DDR2:

1. 8bit prefetching design, while DDR2 is 4bit prefetching, so that the DRAM core frequency is only 1/8 of the interface frequency, and the core of the DDR3-800 operates at a frequency of only 100MHz.

2. Adoption of point-to-point topology to reduce the burden on the address/command and control buses.

3. Adopting a sub-100nm production process, reducing the operating voltage from 1.8V to 1.5V, and adding asynchronous reset and ZQ calibration.

4. The number of logic banks has changed. 4Bank and 8Bank designs in DDR2 SDRAM are designed to cope with the future demand for high-capacity chips. DDR3 will likely start with 2Gb of capacity, so the starting logic bank will be 8, and there will be a provision for 16 logic banks in the future.

5. Packaging changes: DDR3 will have more pins due to new features, 8-bit chips in 78-ball FBGA packages, 16-bit chips in 96-ball FBGA packages, and DDR2 in 60/68/84-ball FBGA packages. And DDR3 must be in a green package and cannot contain any harmful substances.

Second, DDR3 and DDR2 several major differences:

1. Burst Length (BL)

Since DDR3 prefetching for 8bit, so the burst transmission period (Burst Length, BL) is also fixed to 8, and for the DDR2 and the early DDR architecture system, BL For DDR2 and early DDR architecture systems, BL=4 is also commonly used. DDR3 adds a 4-bit Burst Chop mode for this purpose, i.e., a BL=4 read operation is added to a BL=4 write operation to synthesize a BL=8 data burst transfer, which can be controlled via the A12 address line at that time. It should also be noted that any burst interrupt operations will be disabled and not supported in DDR3 memory, and will be replaced by more flexible burst transfer control (e.g., 4-bit sequential bursts).

2. Addressing Timing

Just as the number of latency cycles increased with the transition from DDR2 to DDR, so too will the CL cycles of DDR3 be increased compared to DDR2, which had a CL range of 2 to 5, compared to DDR3's range of 5 to 11, and the design of the additional latency (AL) has changed. The range of AL is 0 to 4, whereas with DDR3 there are three options for AL, 0, CL-1, and CL-2. Additionally, DDR3 has a new timing parameter, write delay (CWD), which will be based on the specific operating frequency.

3. DDR3's new Reset function

Reset is an important new feature of DDR3, and a pin has been dedicated to it; the DRAM industry has been asking for it for a long time, and now it's finally available on DDR3. This pin will make the initialization process of the DDR3 easy. When the Reset command is active, the DDR3 memory stops all operations and switches to a minimally active state to conserve power.

During Reset, the DDR3 memory will shut down most of its intrinsic functions, all data receivers and transmitters will be turned off, all internal program devices will be reset, the DLL (Delayed Phase Locked Loop) and clock circuits will be disabled, and any movement on the data bus will be ignored. This will allow the DDR3 to achieve maximum power savings.

4. DDR3's new ZQ calibration feature

ZQ is also a new pin that has a 240-ohm low-tolerance reference resistor connected to it. This pin automatically calibrates the data output driver on-resistance against the ODT termination resistor value via an on-chip calibration engine (ODCE) via a command set. When the system issues this command, the on-resistance and ODT resistance are recalibrated with the appropriate clock cycles (512 clock cycles after power-up and initialization, 256 clock cycles after exiting the self-refresh operation, and 64 clock cycles in all other cases).

5. The reference voltage is split into two

In the DDR3 system, the reference voltage signal VREF, which is very important for the memory system operation, will be split into two signals, namely VREFCA for command and address signals and VREFDQ for the data bus, which will effectively improve the signal-to-noise level of the system data bus.

6. Point-to-Point (P2P)

This is an important change to improve system performance and is a key difference between DDR3 and DDR2. In a DDR3 system, a memory controller only deals with one memory channel, and that memory channel can only have one slot, so the relationship between the memory controller and the DDR3 memory module is either a Point-to-Point (P2P) relationship (for modules with a single physical Bank) or a Point-to-Two-Point (P22P) relationship (for modules with a dual physical Bank module), thus greatly reducing the load on the address/command/control and data buses. As for memory modules, similar to the DDR2 category, there are standard DIMMs (desktop PCs), SO-DIMMs/Micro-DIMMs (notebook

PCs), and FB-DIMM2 (servers), where the second-generation of FB-DIMMs will feature the higher-specification AMB2 (Advanced Memory Buffer).

DDR3, which is geared toward 64-bit architectures, clearly has more advantages in terms of frequency and speed, and in addition, thanks to a number of other features, such as automatic self-refresh based on temperature and localized self-refresh, that DDR3 employs, DDR3 is much better in terms of power consumption, and so it is likely to be welcomed first in mobile devices, just as it was not desktops that were the first to greet DDR2 memory, but servers. The same goes for servers. The future is also bright for DDR3 in the PC desktop space, where CPU outclocking is increasing most rapidly. Intel's new chipset, Bear Lake, will support DDR3, while AMD is expected to support both DDR2 and DDR3 on the K9 platform.

Four, DDR4

DDR4 Memory Summit

According to reports, the U.S. JEDEC will soon launch the DDR4 Memory Summit, which will mark the beginning of the development of the DDR4 standard. It's thought that new products will hit the market in about 3 years after such a meeting, which means we'll probably be using DDR4 memory in 2011, or as early as 2010.

JEDEC said it considered DDR4 memory at MEMCON07 San Jose, a memory conference held in the U.S. in July, to continue the DDR3 memory specification as much as possible. The use of Single-ended Signaling (SE) signaling means that 64-bit memory module technology will continue. But at the time of the DDR4 Summit, DDR4 memory was said to be more than just Single-ended Signaling, with DDR4 memory based on the Differential Signaling Memory Standard also being introduced at the conference.

DDR4 specifications

So DDR4 memory will have two specifications. DDR4 memory using Single-ended Signaling has been confirmed to have a transfer rate of 1.6-3.2Gbps, while DDR4 memory based on Differential Signaling will have a transfer rate of 6.4Gbps. Since it is essentially impossible to implement both interfaces in a single DRAM, DDR4 memory will have both the traditional SE signaling and differential signaling based interfaces. Since it is essentially impossible to implement both interfaces in a single DRAM, DDR4 memory will be available in both conventional SE signaling and differential signaling based specifications.

According to a number of semiconductor industry stakeholders, DDR4 memory will be Single-ended Signaling (SE) and Differential Signaling (DS). Mr. Phil Hester of AMD also confirmed this. It is expected that the two standards will launch different chip products, so we will see two incompatible memory products in the DDR4 memory era

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