Virtual Addresses for X64

Despite the 64-bit width of virtual addresses, current implementation mechanisms (and any chips known to be in the planning stage) do not allow the entire 16EB of virtual address space to be used. Most operating systems and applications won't be able to use such a large address space for the foreseeable future (for example, the Windows implementation on AMD64 applies only 16TB, or 44 bits, of width), so implementing such a large address width would only add complexity and address translation costs to the system, with no benefit. AMD has therefore decided that in the first implementation of this architecture, only the lowest 48 bits of a virtual address will be used for address translation (page table lookup). However, bits 48 through 63 of any virtual address must match bit 47 (in the manner of sign bit expansion) or the processor will report an exception. Addresses that conform to this rule are called "Canonical Addressing". The canonical form of addressing treats the address range from 0 to 00007FFF`FFFFFFFFFFF, and from FFFFF8000`000000 to FFFFFFFF`FFFFFFFFFFF totaling 256 terabytes as the virtual address space that can be used.

This "quirky" rule preserves an important feature for future extensions to true 64-bit addressing: many operating systems (including, but not limited to, the Windows NT family) reserve the upper half of the address space (called kernel space) for themselves, and the lower half (user space) for the application. program code, the user stack, the heap, and other data areas. This "traditional address" design ensures that every AMD64-compliant implementation has two memory segments: the lower half starts at 00000000`00000000 and "grows upwards" as more virtual address bits become available; the upper half is "grown upwards" as more virtual address bits become available; and the upper half is "grown upwards" as more virtual address bits become available. "The high half is "suspended" at the top of the address space and "grows down". Similarly, the unused address bit content is held in place to prevent it from being used by the operating system for flags, privilege levels, and other purposes, in order to avoid problems when the architecture scales to 52, 56, 60, and 64 bits.

The 64-bit addressing mode (long mode), is a superset of Physical Address Extension (PAE); as such, memory page sizes can be 4KB, 2MB, or 1GB. however, unlike the three-level tabbed table mechanism that the system uses in PAE mode, the system uses a four-level tabbed table in long mode: the PAE's page directory pointer table has been expanded from four to 512 table entries and a fourth level Page-Map Level 4 Table (PML4 Table) is appended, containing 512 table entries using a 48-bit implementation. In implementations that provide larger virtual addresses, this table can either be extended to provide a sufficient number of table entries (up to 33,554,432 theoretically for a 64-bit implementation) to describe the entire address space, or it can be mapped by a higher mapping level, such as PML5. The full 4KB page-mapping level for the entire 48-bit address space would take up a little over 512GB of memory (256TB of virtual address space). memory (0.196% of the 256TB virtual address space).