STDcell simulation test process

①According to the PDK file provided by funder, first add the STDcell symbol library path in cadence library manager (you can also directly add the symbol library path in cds.lib). After this step, the STDcell symbol and schematic should also be imported into the corresponding STDcell cellview.

② Find the GDS file of the STDcell, stream In the GDS into the STDcell symbol library, and merge it into a library.

① Replace the CellName.txt path with the path of the current STDcellName list. csm18ic with the path of the current STDcellName library. Replace csm18ic at csm18ic with current STDcell library name.

The list document of STDcellName is in the following format:

① Load "********/copyView.il" in cadence CIW. refresh library ". refresh library to see the STDcell's cellView under the generation of a spectre .

③ Add port information to each STDcell's spectre.

③ Add port information to each STDcell spectre.

In the above figure, replace CellName.txt path with the path of the current STDcellName list, CellPort.txt path with the path of the current STDcellPort list, and csm18ic with the current STDcell library name.

④ Replace the current STDcell library name in the cellView of the STDcell by the current STDcell library name. p>

④ Load "********/fillPort.il" in cadence CIW. refresh library to see the STDcell's cellView with port information for each spectre.

Run simulation

①Modify the power and ground information in the cdl of STDcell. Sometimes the cdl uses 1 for power and 0 for ground, then you need to change 1 to vdd! and 0 to gnd! (the names in the circuit should be exactly the same as the case in the cdl). power and ground in the STDcell must be set globally. The following cdl example:

② Create an inverter schematic test. The following is an example of a cdl test:

③ Enter the analog design environment in launch->ADE L, click Setup->Model libraries, and set the lib information and the cdl of the STDcell. STDcell cdl information. Click OK to run the simulation. The settings are as follows:

④View the output signal waveform to check whether the result is correct. In Results->Direct Polt->Main Form the following figure shows the square wave output signal graph:

① Filter out STDcellName.txt in STDcell.cdl;

$grep 'SUBCKT' STDcell.cdl >test. txt

$cat test.txt| awk '{print $1}' >STDcellName.txt

② Filter STDcellPort.txt in STDcell.cdl;

$cat test.txt| awk '{print $1,$ 2,$3,$4......}'>STDcellPort.txt

(the value of the maximum number of pins in cdl is used as the value of the maximum $ in the print output, "," means that each pin is separated by a spaces to separate them, and cannot be omitted).

③ When encountering the problem of converting information from different versions of cadence. The symbol lib information of this project is CDB to OA.

Create a folder in cadence, such as CDB. put the libs that need to be loaded and switched in this folder, create a cds.lib, and add all the libs that need to be converted to this file in the following format:

DEFINE ?library_name ?library_path

In cadence61 version CIW, Tools->Conversion Tool Box->CDB to OpenAccess Translator