Graphene chip and traditional silicon chip

Based on silicon-based transistors, the current mainstream transistor architectures can be divided into fin field effect transistors and surrounding gate transistors; However, the gate size of industrial transistors is above 12 nm. In this context, chip companies hope to achieve higher-tech chip manufacturing, and it is common to improve the accuracy of mask aligners and improve and optimize the transistor architecture. In fact, it is also a feasible scheme to improve the chip performance by shortening the gate size of transistors and increasing the number of transistors.

Why do you bring this up? Of course, because we have the technology of the third scheme. That is, by shortening the transistor gate size, the chip performance is improved in phase. On March 12, 2022, Tsinghua University broke through the technical bottleneck of the ice-breaking industry, and realized the transistor with sub-1 nanometer gate length for the first time, and on this basis, it has good electrical properties.

According to the news from official website, Tsinghua University, the team led by Professor Ren from the Institute of Integrated Circuits has made a major breakthrough in the research of small-size transistors. The transistor with sub 1 nm gate length has been successfully transformed. Generally speaking, the shorter the gate length of the transistor, the more transistors can be accommodated in the silicon-based chip architecture. If there is a way to realize the inverse ratio between the gate length and the chip performance, that is, the charging performance, then we can completely reduce the requirements for mask aligner process.

More importantly, according to the news from official website, Tsinghua University, the sub- 1 nano-gate-length transistor introduced by the team has good electrical performance. This means that the scheme of reducing or avoiding the dependence on the EUV mask aligner by shortening the transistor gate length is expected to be realized. Maybe some friends will say that we thought of shortening the transistor gate length to improve the chip performance, but foreign countries didn't think of it? A: Foreign countries can think of it, but the technology, performance and dynamic stability are not as high as ours.

In fact, as early as 20 12, Japan realized the equivalent 3 nm planar unstructured silicon-based transistor. In 20 16, a planar molybdenum sulfide transistor with physical gate length 1 nm was realized in the United States. The physical gate length of the sub- 1 nano-gate transistor realized in Tsinghua University is 0.34 nm. Compared with Japanese and American semiconductors, obviously our accuracy is higher. Is it only accurate? Of course not!

Firstly, the shortcomings of equivalent 3 nm and 1 nm physical gate transistors introduced by Japan and the United States at 20 12 and 20 16 respectively are analyzed. The equivalent 3 nm planar unstructured silicon-based transistor introduced by Japan in 20 12 was shelved because of its immature architecture and unstable transistor performance. The planar molybdenum sulfide transistor with physical gate length 1 nm introduced by the United States has relatively stable and reliable architecture support, but there are problems in the selection of raw materials. That is, sulfur with extremely poor stability is used as raw material.

Tsinghua University's research team skillfully utilized the existing technical advantages, and used the ultra-thin single-layer thickness and excellent conductivity of graphene film as the gate to realize the vertical Mo S2 channel switching based on the transverse electric field of graphene. On the basis of ensuring the stability of performance and electric field, a physical gate transistor structure equivalent to 0.34 nm is realized.

Interestingly, when it comes to graphene technology, we are the "grandfathers" of the West. That is, as early as 2020, we realized the commercial mass production of 8-inch and 12-inch graphene sheets. But it also explains why foreign countries gradually give up reducing the gate length because of the lack of mature raw material technology. As for graphene, I think you have heard many reports about this raw material earlier. Under the same process, the performance of graphene chip is 5~ 10 times that of silicon-based chip. As for the authority, the IEEE global authoritative semiconductor organization gave confirmation. In other words, graphene materials are expected to become the key raw materials to continue Moore's Law in the future.

Come back to Tsinghua. The 0.34 nm physical gate transistor successfully broken through by the research team completes the electric field shielding in the vertical direction of graphene by depositing metal on the surface of graphene and naturally oxidizing it. That's not all. In order to further improve the stability of the transistor, Tsinghua's team also used hafnium carbon dioxide deposited by atomic layer as the gate dielectric, and a single-layer two-dimensional molybdenum disulfide film deposited by chemical vapor deposition as the channel.

It is worth mentioning that in order to effectively control the vertical molybdenum disulfide through the electric field at the edge of graphene, Tsinghua University's research team also adopted the process-based computer aided design (TCAD). At present, the research results have been published in the top international academic journal Nature. This also dispelled some people's doubts and speculations about this achievement.

Generally speaking, the breakthrough research results of Tsinghua University are expected to help us achieve our independent goals in the field of high-end chips in the future. I hope Tsinghua University will launch and implement this technology as soon as possible. Realize the transformation from laboratory to factory application as soon as possible.

What do you want to say about the equivalent 0.34 nm physical gate length transistor that Tsinghua University successfully broke the ice? In the future, if we want to achieve parity catch-up in the semiconductor field through graphene, we will inevitably encounter many problems. Including infrastructure and personnel training. Do you have any good opinions and suggestions on this?

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